 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| FUJITSU SEMICONDUCTOR DATA SHEET DS04-22420-3E ASSP Communication Control CMOS FAST-20 SCSI Protocol Controller MB86606A s DESCRIPTION The MB86606A is an intelligent SCSI protocol controller (SPC) conforming to the ANSI (FAST-20) standard and integrating a PCI local bus interface function. The specification of SCSI controller block is based on the MB86605's one which is a Wide SCSI protocol controller, but the device functions/features to achieve the FAST-20 data transfer rate of maximum 40 Mbyte/sec at 16-bit FAST-20 SCSI, such as the size of internal data register FIFO, are larged on the MB86606A. As for the SCSI bus pins, a totem pole type single-ended driver/ receiver is incorporated in the device so that it can drive the SCSI bus directly. Furthermore, the MB86606A is capable of connecting the external differential type driver/receiver. The SCSI bus sequence is controlled by commands issued via the system interface. So, it supports sequential commands that perform the phase-to-phase sequences to reduce the overhead of system's sequence operations. As another key feature to reduce the system overhead, the device has a 2 Kbytes user program memory to store the user program with the commands. Due to this, all the SCSI bus sequences including the data transfer can be performed automatically. As the system interface block, it incorporates a 32-bit PCI local bus interface that easily realizes the SCSI interface on the motherboards of PCI bus based PCs and WSs, in addition to a 16-bit separate MPU and DMA buses. For the on-chip PCI bus interface, the MB86606A also incorporates a 32-bit DMA controller that is capable of supporting the scatter-gather function so that the data transfers can be controlled by both user program and the host system. The device is fabricated by the advanced CMOS process and is housed in an 144-pin plastic Quad Flat Package (Suffix: -PMT2). s PACKAGE 144 pin plastic LQFP (FPT-144P-M08) MB86606A s FEATURES SCSI Protocol Controller Block: * Operable as initiator and target * WIDE and FAST-20 data transfers Synchronous transfer (max. 40 Mbytes/s: Up to 256 offset values can be set.) Asynchronous transfer (max. 10 Mbytes/s) * 512-byte FIFO register for data phase * Two types (send-only and receive-only) of 32-byte data buffers for message, command, and status phases (MCS Buffers) * On-chip totem pole type SCSI single-ended driver/receiver * Supports external SCSI differential driver/receiver connectivity * On-chip memory to store transfer parameters for each ID (up to 15 connected devices) * On-chip 16-bit transfer block counter and 24-bit transfer byte counter Maximum Transfer Byte : 1 Tbyte at fixed length data transfer : 16 Mbyte at variable length data transfer * Supports various control commands: Sequential Commands : can perform phase-to-phase sequential operations (functions only when issuing from a system side.) Discrete Commands : can perform any desired sequence to program in the user program memory Data Transfer Commands : can program the transfer data length at the user program operation. * On-chip direct control register for SCAM (SCSI Configured AutoMatically) Level-1 Protocol * Supports Multi Selection/Reselection Responses Selection and Reselection responses can be done to plural IDs. * On-chip 2 Kbyte User Program Memory Two Modes : 2 Kbyte x 1 bank and 1 Kbyte x 2 banks (While 1 Kbyte x 2 banks are selected, host system can access another bank even if the user program is executing.) Access to User program : Burst transfer via I/O access port : Direct access to 2 Kbyte user program memory (only for PCI bus I/F mode) * User Selectable Interrupt Report Unnecessary interrupt reports can be disabled depending on user's applications to reduce a system ISR overhead. * Two automatic receive modes Initiator : can automatically receive information for new phase to which target switched Target : can automatically receive attention condition generated by initiator * Automatic selection/reselection For command issues : automatically performs to receive MSG/CMD to the selection/reselection request from partner device For user program operation : pauses the program currently executed and automatically jumps to the specified selection /reselection routine in response to the selection/reselection request from partner device. * Operation Clock System Clock: Max. 40 MHz Internal Processor Operating Clock: Max. 20 MHz (Continued) 2 MB86606A (Continued) System Interface Block: * Separate MPU and DMA buses called 16-bit Bus Mode Directly connectable to 68-series or 80-series MPU Two transfer modes (Program transfer and DMA transfer (slave mode)) * PCI Bus Interface Mode Directly connectable to the 32-bit PCI local bus. On-chip 32-bit DMAC for PCI bus master Supports the PERR&SERR function Supports the INTA# Interrupt Signals Max. 64 bytes burst transfer PCI system clock: Max. 33 MHz * Data Bus Parity and Address Bus Parity (only for PCI bus interface mode) generation/check function Others * Compact 144-Pin Plastic Quad Flat Package (LQFP Package Suffix: -PMT2) , * Pin compatible with MB86605 * Supply Voltage: 5V 5% 3 4 MB86606A * 16-Bit Bus Mode s PIN ASSIGNMENT 40 140 INDEX 45 135 50 130 55 125 DMD9 V SS DMD8 DMD7 DMD6 V DD DMD5 V SS DMD4 DMD3 DMD2 V SS DMD1 DMD0 LDMDP V SS UDP V DD D15 D14 V SS D13 D12 D11 V SS D10 D9 D8 D7 V SS V DD D6 D5 D4 V SS D3 5 1 35 144 (TOP VIEW) 30 25 20 15 10 (FPT-144P-M08) 120 115 110 100 105 75 80 85 90 95 LDBOEP V DD DB12 DB13 DB14 DB15 V SS UDBP DB0 DB1 V SS DB2 DB3 DB4 DB5 V SS DB6 DB7 LDBP ATN V SS BSY ACK RST MSG SEL V SS C/D REQ I/O DB8 V SS DB9 DB10 DB11 V DD 60 65 D2 D1 D0 V SS LDP UDS/BHE V DD LDS/WR V SS R/W/RD CS1 CS0 V DD INT A4 A3 V SS SCLK A2 A1 A0 V SS MODE1 MODE0 S/DSEL TARG V DD INIT SELOE V SS RSTOE BSYOE DBOE11 DBOE10 DBOE9 DBOE8 70 DMD10 DMD11 DMD12 DMD13 V SS DMD14 DMD15 V DD UDMDP DMR/W/DMRD V SS DMLDS/DMWR DMUDS/DMBHE V DD DREQ DACK V SS RESET TP DMA0 DBOE12 DBOE13 V SS DBOE14 DBOE15 UDBOEP DBOE0 DBOE1 V DD DBOE2 DBOE3 DBOE4 V SS DBOE5 DBOE6 DBOE7 MB86606A * PCI Bus Interface Mode (TOP VIEW) IDSEL C/BE3 AD24 AD25 V SS AD26 AD27 V DD AD28 AD29 V SS AD30 AD31 V DD PREQ GNT V SS RESET PCLK SERR DBOE12 DBOE13 V SS DBOE14 DBOE15 UDOBEP DBOE0 DBOE1 V DD DBOE2 DBOE3 DBOE4 V SS DBOE5 DBOE6 DBOE7 140 135 130 125 120 115 1 110 40 45 50 55 60 65 C/BE0 AD7 AD6 V SS AD5 AD4 V DD AD3 V SS AD2 AD1 AD0 V DD INT PO1 PO0 V SS SCLK PI1 PI0 N. C. V SS MODE1 MODE0 S/DSEL TARG V DD INIT SELOE V SS RSTOE BSYOE DBOE11 DBOE10 DBOE9 DBOE8 (FPT-144P-M08) 70 AD23 V SS AD22 AD21 AD20 V DD AD19 V SS AD18 AD17 AD16 V SS C/BE2 FRAME IRDY V SS TRDY V DD DEVSEL STOP V SS PERR PAR C/BE1 V SS AD15 AD14 AD13 AD12 V SS V DD AD11 AD10 AD9 V SS AD8 105 5 INDEX 100 10 95 15 90 20 85 25 80 30 75 35 LDBOEP V DD DB12 DB13 DB14 DB15 V SS UDBP DB0 DB1 V SS DB2 DB3 DB4 DB5 V SS DB6 DB7 LDBP ATN V SS BSY ACK RST MSG SEL V SS C/D REQ I/O DB8 V SS DB9 DB10 DB11 V DD 5 MB86606A s PIN LIST 16-bit bus mode PCI bus I/F mode 16-bit bus mode PCI bus I/F mode Pin Pin no. Mode 0 (68 I/F) Mode 1 (80 I/F) Mode 3 (PCI I/F) no. Mode 0 (68 I/F) Mode 1 (80 I/F) Mode 3 (PCI I/F) I/O Pin name 1 2 3 4 5 6 7 8 9 I/O DMD9 -- VSS I/O DMD8 I/O DMD7 I/O DMD6 -- VDD I/O DMD5 -- VSS I/O DMD4 I/O AD18 I/O AD17 I/O AD16 I/O C/BE2 I/O FRAME I/O IRDY I/O TRDY I/O DEVSEL I/O STOP I/O AD19 I/O AD22 I/O AD21 I/O AD20 I/O Pin name I/O Pin name I/O AD23 31 I/O Pin name I/O Pin name I/O -- VDD I/O AD11 I/O AD10 I/O AD9 I/O AD8 I/O C/BE0 I/O AD7 I/O AD6 I/O AD5 I I I BHE WR RD I/O AD4 I/O AD3 I/O AD2 I/O AD1 I/O AD0 32 I/O D6 33 I/O D5 34 I/O D4 35 -- VSS 36 I/O D3 37 I/O D2 38 I/O D1 39 I/O D0 40 42 43 44 45 46 47 48 49 50 51 I/O PERR I/O PAR I/O C/BE1 I/O AD15 I/O AD14 I/O AD13 I/O AD12 52 53 54 55 56 57 58 59 60 -- VSS I I I I I O/ OD Pin name 10 I/O DMD3 11 I/O DMD2 12 -- VSS 13 I/O DMD1 14 I/O DMD0 15 I/O LDMDP 16 18 -- VSS -- VDD 17 I/O UDP 19 I/O D15 20 I/O D14 21 -- VSS 41 I/O LDP UDS LDS R/W CS1 CS0 -- VDD -- VSS -- VDD INT A4 A3 SCLK IU PI1 IU PI0 IU N.C. O O PO1 PO0 I I I 22 I/O D13 23 I/O D12 24 I/O D11 25 -- VSS 26 I/O D10 27 I/O D9 28 I/O D8 29 I/O D7 30 -- VSS -- VSS IU A2 IU A1 IU A0 -- VSS I I MODE1 MODE2 (Continued) 6 MB86606A (Continued) 16-bit bus mode Pin Pin no. Mode 0 (68 I/F) Mode 1 (80 I/F) Mode 3 (PCI I/F) no. Mode 0 (68 I/F) Mode 1 (80 I/F) Mode 3 (PCI I/F) I/O Pin name 61 62 63 64 65 66 67 68 69 70 71 72 73 I O O O O O O O O O S/DSEL TARG INIT SELOE RSTOE BSYOE DBOE11 DBOE10 DBOE9 DBOE8 I/O Pin name I/O Pin name 91 92 93 94 95 96 97 98 99 I/O Pin name I/O Pin name I/O I/O DB7 I/O DB6 -- VSS I/O DB5 I/O DB4 I/O DB3 I/O DB2 -- VSS I/O DB1 Pin name PCI bus I/F mode 16-bit bus mode PCI bus I/F mode -- VDD -- VSS 100 I/O DB0 101 I/O UDBP 102 -- VSS 103 I/O DB15 104 I/O DB14 105 I/O DB13 106 I/O DB12 107 -- VDD 108 109 110 111 113 114 115 117 118 119 120 O O O O O O O O O O O LDBOEP DBOE7 DBOE6 DBOE5 DBOE4 DBOE3 DBOE2 DBOE1 DBOE0 UDBOEP DBOE15 -- VDD 74 I/O DB11 75 I/O DB10 76 I/O DB9 77 -- VSS 78 I/O DB8 79 I/O I/O 80 I/O REQ 81 I/O C/D 82 -- VSS 83 I/O SEL 84 I/O MSG 85 I/O RST 86 I/O ACK 87 I/O BSY 88 -- VSS 89 I/O ATN 90 I/O LDBP 112 -- VSS 116 -- VDD (Continued) 7 MB86606A (Continued) 16-bit bus mode Pin Pin no. Mode 0 (68 I/F) Mode 1 (80 I/F) Mode 3 (PCI I/F) no. Mode 0 (68 I/F) Mode 1 (80 I/F) Mode 3 (PCI I/F) I/O Pin name 121 O DBOE14 122 -- VSS 123 O DBOE13 124 O DBOE12 125 126 127 129 I I I I DMA0 TP RESET DACK I GNT OD SERR I PCLK I/O Pin name I/O Pin name 133 135 I/O Pin name I/O Pin name I/O I I DMLDS DMR/W I I DMWR DMRD 134 -- VSS I/O AD29 I/O AD28 I/O AD27 I/O AD26 I/O AD25 I/O AD24 I/O C/BE3 I IDSEL 136 I/O UDMDP 137 -- VDD 138 I/O DMD15 139 I/O DMD14 140 -- VSS 141 I/O DMD13 142 I/O DMD12 143 I/O DMD11 I DMBHE I/O AD31 144 I/O DMD10 O PREQ Pin name I/O AD30 PCI bus I/F mode 16-bit bus mode PCI bus I/F mode 128 -- VSS 130 O DREQ 131 -- VDD 132 I DMUDS I : Input pin O : Output pin I/O : Input/Output pin IU : Input pin with pull-up resistor OD : Open-drain output pin 8 MB86606A s PIN DESCRIPTION 1. SCSI Interface Pin no. Pin name I/O Function 84, 81 89, 79 MSG, C/D ATN, I/O These are the SCSI control signal input and output pins. They can be connected directly to a single-ended I/O SCSI connector. Either open-drain or totem pole output can be selected. These are the SCSI control signal input and output pins. I/O They can be connected directly to a single-ended SCSI connector. The output buffer is the totem pole type. O These are used for output control of SCSI control signals. They should be used as control signals for the external differential driver/receiver circuit. 80, 86 REQ, ACK 68 65 67 87 83 85 120, 121, 123, 124, 69 to 72 119 109 to 111, 113 to 115, 117, 118 108 103 to 106, 74 to 76, 78 101 91, 92, 94 to 97, 99, 100 90 BSYOE SELOE RSTOE BSY SEL RST DBOE15 to DBOE8 UDBOEP DBOE7 to DBOE0 LDBOEP DB15 to DB8 UDBP DB7 to DB0 LDBP These are the SCSI control signal input and output pins. I/O They can be connected directly to a single-ended SCSI connector. The output buffer is the open-drain type. These are used for output control of SCSI data bus signals. They should be used as control signals for the external differential driver/receiver circuit. O These are used to input and output SCSI data bus signals. They can be connected directly to a single-ended I/O SCSI connector. Either open-drain or totem pole output buffer can be selected. O These are used to output signals indicating the chip operating status. They should be used as control signals for the external differential driver/receiver circuit. This is used to input signal for selecting the chip operation mode. Single-ended: Input 0 Differential-ended: Input 1 While 0 is input to this pin, all the SCSI control signals, data bus output control signals, INIT, and TARG signals are fixed with L level. This pin is used for a system clock input for SCSI protocol controller block. (Max. 40 MHz) 64 62 INIT TARG 61 S/DESL I 54 SCLK I 9 MB86606A 2. 16-Bit Bus Mode-MPU Interface Pin no. 48 47 19, 20, 22 to 24, 26 to 28 17 29, 32 to 34, 36 to 39 41 51, 52, 55 to 57 Pin name CS0 CS1 D15 to D8 UDP D7 to D0 LDP A4 to A0 I/O I I Function This is used to input signals for the MPU to select the SPC as the I/O device. This is used to input select signals (external circuit select signals) for the MPU to input and output the DMA data bus data via the SPC. Upper byte and parity of data bus When CS0 input valid: I/O ports for internal registers in SPC When CS1 input valid: I/O ports for DMA bus data Lower byte and parity of data bus When CS0 input valid: I/O ports for internal registers in SPC When CS1 input valid: I/O ports for DMA bus data These are used to input addresses for selecting the Internal registers. In 80-series mode: This is used to input the read strobe signal for reading data from the SPC to the MPU. In 68-series mode: This is used to input the R/W control signal for reading and writing data from the MPU to the SPC. In 80-series mode: This is used to input the write strobe signal for writing data from the MPU to the SPC. In 68-series mode: This is used to input the LDS signal output by the MPU when the lower byte of the data bus is valid. In 80-series mode: This is used to input the BHE signal output by the MPU when the upper byte of the data bus is valid. In 68-series mode: This is used to input the UDS signal output by the MPU when the upper byte of the data bus is valid. I/O I/O IU 46 RD (R/W) I 44 WR (LDS) I 42 BHE (UDS) I 10 MB86606A 3. 16-Bit Bus Mode - DMA Interface Pin no. 130 Pin name DREQ I/O O Function This is used to output DMA transfer request signals to the DMAC. DMA data transfer between the SPC and memory is requested. This is used to input DMA-enabling signals from the DMAC. When the DMA enabling signal is active, DMA reading and writing are executed. 129 DACK I 138, 139, 141 to 144, 1, 3 DMD15 to 8 136 UDMDP Upper byte and parity of DMA data bus When CS1 input valid: The MPU data bus is directly I/O connected. When 80-series mode: The 2nd data is input/output. When 68-series mode: The 1st data is input/output. Lower byte and parity of DMA data bus When CS1 input valid: The MPU data bus is directly I/O connected. When 80-series mode: The 1st data is input/output. When 68-series mode: The 2nd data is input/output. In 80-series mode: This is used to input the IORD or RD signal for outputting data from the SPC to the DMA bus. In 68-series mode: This is used to input the R/W control signal for outputting and inputting data from the DMAC to the SPC. In 80-series mode: This is used to input the IOWR or WR signal for inputting data from the DMA bus to the SPC. In 68-series mode: This is used to input the LDS signal output by the DMAC when the lower byte of the DMA data bus is valid. In 80-series mode: This is used to input the BHE signal output by the DMAC when the upper byte of the DMA data bus is valid. In 68-series mode: This is used to input the UDS signal output by the DMAC when the upper byte of the DMA data bus is valid. This is used to input the address data A0 signal output by the DMAC in the 80-series mode. In 68-series mode: Connect to power supply pin (VDD). This is used to input DMA-transfer-enabling signals. When the TP signal is active, the SPC performs the DMA transfer. When this signal becomes inactive during DMA transfer, the transfer stops temporarily at the block boundary. 4, 5, 7, 9 to 11, 13, 14 15 DMD7 to 0 LDMDP 135 DMRD (DMR/W) I 133 DMWR (DMLDS) I 132 DMBHE (DMUDS) I 125 DMA0 I 126 TP (Transfer permission) I 11 MB86606A 4. PCI Bus Interface Mode Pin no. 130 129 Pin name PREQ GNT I/O O I Function This pin is used to request the bus arbiter for use of the bus. This is the response signal input pin to the REQ signal from the bus arbiter. 132, 133, 135, 136, 138, 139, 141, 142, 1, 3 to 5, 7, 9 to 11, 26 to 29, AD31 to AD0 32 to 34, 36, 38, 39, 41, 42, 44, 46 to 48 143, 13, 24, 37 23 14 17 15 20 C/BE3 to C/BE0 PAR FRAME TRDY IRDY STOP I/O PCI 32-bit address and data multiplexed pins I/O Bus command and Byte Enable signals multiplexed pins. This is an even parity signal pin for the AD31 to AD0 and C/ I/O BE3 to C/BE0 signals. This PAR signal becomes valid after one clock. I/O This is a frame signal pin that indicates data are transferring on the bus. I/O Data Ready signal of Target side. I/O Data Ready signal of Initiator (Bus master) side. I/O This is a stop request signal to stop the data transfer from target to master. 19 DEVSEL Device select pin. While the device is a target, this pin outputs the select signal that indicates the self device is I/O selected. While the device is a master this pin functions as an input pin to indicate that a device on the bus is selected. I I This is a chip select signal that indicates the configuration access. PCI bus clock input pin. The maximum clock frequency is 33 MHz. 144 126 22 125 IDSEL PCLK PERR SERR I/O Data parity error input and output pin. OD Address parity error output pin. 12 MB86606A 5. Other Signals Pin No. 127 Pin name RESET I/O O Function This pin is used to input system reset signals. These pins are used for setting the device operation mode as listed in the table below. MODE1 MODE0 0 59, 60 MODE1, MODE0 I 0 1 1 0 1 0 1 Operation Mode 16-bit bus mode (68 series mode) 16-bit bus mode (80 series mode) Reserved PCI bus interface mode 50 INT Interrupt output pin. Either totem pole or open-drain output O/ buffer can be selected. This pin has an internal pull-up OD resistor. -- Power supply pin 6, 18, 31, 43, 49, 63, VDD 73, 107, 116, 131, 137 2, 8, 12, 16, 21, 25, 30, 35, 40, 45, 53, 58, 66, 77, 82, 88, 93, 98, 102, VSS 112, 122, 128, 134, 140 51, 52 PO1, PO0 -- Ground pin O General purpose output ports that can control the external active SCSI bus terminator etc. Initial signal level on each pin is "L". Those pins are available only for PCI bus interface mode. General purpose input ports. Available only for PCI bus interface mode. 55, 56 57 PI1, PI0 N.C. IU No connection and unused pins. These pins exist on the only -- PCI bus mode. These are internally pulled-up, and do not connect to the pins. I : Input pin O : Output pin I/O : Input and Output pin OD : Open-drain output pin IU : Input pin with pull-up resistor 13 MB86606A s BLOCK DIAGRAM 1. 16-Bit Bus Mode D15 to 8, UDP D7 to 0, LDP MPU Interface MSG C/D I/O ATN BSYOE BSY 2 SELOE SEL RSTOE RST SCSI Interface 3 Phase Controller 7 4 Transfer Controller Send MSG, CMD, Status Buffer DMA Interface DMD15 to 8, UDMAP DMD7 to 0, LDMDP (32 Bytes) DMA0 Timer 6 (32 Bytes) DREQ DACK DMBHE (DMUDS) 1 Internal Processor 5 Various Registers Receive MSG, CMD, Status Buffer REQ ACK INIT TARG 8 (2048 Bytes) User Program Memory BHE (UDS) WR (LDS) RD (R/W) A4 to 0 CS0 CS1 INT IOWR (DMLDS) DB15 to 8, UDBP DB7 to 0, LDBP IORD (DMR/W) 9 (512 Bytes) DBOE15 to 8, UDBOEP DBOE7 to 0, LDBOEP S/DSEL Data Register TP 14 MB86606A 2. PCI Bus Interface Mode C/BE3 to 0 AD31 to 0 DEVSEL FRAME IDSEL PREQ PERR SERR STOP TRDY PCI Interface MSG C/D I/O ATN BSYOE BSY 2 SELOE SEL RSTOE RST SCSI Interface 3 Phase Controller 7 4 Transfer Controller Send MSG, CMD, Status Buffer DMA Controller (32 Bytes) Timer 6 (32 Bytes) 1 Internal Processor 5 Various Registers Receive MSG, CMD, Status Buffer 11 REQ ACK INIT TARG 8 (2048 Bytes) User Program Memory DB15 to 8, UDBP DB7 to 0, LDBP 9 (512 Bytes) DBOE15 to 8, UDBOEP DBOE7 to 0, LDBOEP S/DSEL Data Register 10 Burst-FIFO (64 Bytes) PCLK IRDY GNT PAR 15 MB86606A s BLOCK FUNCTIONS 1. Internal Processor This processor provides the sequence control between each phase. 2. Timer This timer manages the time specified by SCSI and the following time: * * * * REQ/ACK assertion time for data at asynchronous transfer Selection/reselection retry time Selection/reselection timeout time REQ/ACK timeout time during transfer Asynchronous transfer (target) : Time required for initiator to assert ACK signal after asserting REQ signal Asynchronous transfer (initiator) : Time required for target to negate REQ signal after asserting ACK signal Synchronous transfer (target only) : Time required for target to receive ACK signal for setting offset value to 0 from initiator after sending REQ signal 3. Phase Controller This controller controls the arbitration, selection/reselection, data-in/out, command, status, and message-in/out phases executed on the SCSI bus. 4. Transfer Controller This controller controls the information (data, command, status, message) transfer phases executed on the SCSI bus. There are two types of transfer for executing the information transfer phases. * Asynchronous transfer * Synchronous transfer : Control by interlocking REQ and ACK signals : Control with maximum of 32-byte offset value in data-in/out phase Depending on the data migration, there are the following two modes. * Program transfer : Performed via MPU interface using data registers * DMA transfer : Performed via DMA interface using DREQ and DACK pins At synchronous transfer, the transfer parameters (transfer mode, minimum cycle period of REQ or ACK signal sent from SPC in synchronous transfer, and maximum value between REQ and ACK signals in synchronous transfer) can be saved for each ID and are automatically set when the data phase is started. The transfer byte count is determined by block length x number of blocks. 5. Various Registers * Command register This register specifies each command with an 8-bit code. When using the user program, specify "1" at the Bit 7. The lower 7 bits (Bit 6 to Bit 0) are invalid. * Nexus status register This register indicates the chip's operating condition, the nexused partner's ID, and data register status. * SCSI control signal status register This register indicates the status of SCSI control signals. 16 MB86606A * Interrupt status register This register indicates the interrupt status with an 8-bit code. * Command step register This register indicates the execution status of each command with an 8-bit step code. Error causes can be analyzed by referencing the interrupt status register and this register. * Group 6/7 command length setting register This register sets the group 6/7 command length not defined in the SCSI standard. Setting this register determines the group 6/7 command length. 6. Receive MSG, CMD, Status Buffer (Receive MCS Buffer) This is a 32-byte receive-only information buffer that holds the information for the message, command, and status received from the SCSI bus. 7. Send MSG, CMD, Status Buffer (Send MCS Buffer) This is a 32-byte send-only information buffer that holds the information for the message, command, and status sent on the SCSI bus. 8. User Program Memory This is a 2048-byte program memory that stores programmable commands. It can consist of 1024-byte x 2 banks or 2048-byte x 1 bank. 9. Data Register This is a 512-byte FIFO data register that holds data in the data phase executed on the SCSI bus. 10.Burst FIFO 64-byte FIFO type data buffer to perform burst transfer during the PCI bus interface mode. The device has total 576-byte FIFO with Data Register and Burst FIFO in the PCI bus interface mode. 11.DMA Controller This is a 32-bit DMA Controller that performs data transfer. This DMAC is a bus master during the PCI bus interface mode. 17 MB86606A s ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage* Input voltage* Output voltage* Operating ambient temperature Storage temperature * : The voltages are based on VSS (= 0V) Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Symbol VDD VI VO Top Tstg Rating Min. VSS-0.5 VSS-0.5 VSS-0.5 -25 -40 Max. 6.0 VDD+0.5 VDD+0.5 +85 +125 Unit V V V C C s RECOMMENDED OPERATING CONDITIONS Parameter Supply voltage* SCSI clock input frequency PCI clock input frequency Operating temperature * : The voltages are based on VSS (= 0V) Note: The recommended operating conditions are the recommended values for assuring normal logic operation of the LSI. Requirements in electrical characteristics (DC and AC characteristics) are assured within the range of the recommended operating conditions. Symbol VDD fSCSI fPCI Ta Value Min. 4.75 20.0 -- 0 Typ. 5.0 -- -- -- Max. 5.25 40.0 33.0 +70 Unit V MHz MHz C 18 MB86606A s ELECTRICAL CHARACTERISTICS 1. DC Characteristics (VDD = +5 V5%, VSS = 0 V, Ta = 0 to +70C) Value Symbol Condition Unit Min. Max. VIH VIL VIH VIL VIH VIL 1 Parameter SCSI pins Input voltage*1 SCLK pins SDSEL pins Other pins SCSI-pin input hysteresis* -- -- -- -- -- -- -- IOH = -7.0 mA IOL = +48.0 mA IOL = +48.0 mA IOL = +48.0 mA IOH = -7.0 mA IOL = +48.0 mA IOH = -7.0 mA IOL = +3.2 mA IOH = -2.0 mA IOL = +6.0 mA IOH = -2.0 mA IOL = +3.2 mA VIN = 0 to VDD VIN = 0 to VDD -- 1.9 -- 2.4 -- 2.0 -- 0.3 2.0 -- -- -- 2.0 -- 2.0 -- 4.2 -- 4.2 -- -10 -10 -- -- 1.0 -- 0.8 -- 0.8 -- 3.24 0.5 0.5 0.5 3.24 0.5 3.24 0.4 -- 0.55 -- 0.4 +10 +10 150 V V V V V V V V V V V V V V V V V V V A A mA VHW REQ, ACK VOH VOL VOL VOL VOH VOL VOH VOL VOH VOL VOH VOL ILI ILOZ IDD SCSI pins Output voltage*1 In single- RST, BSY, SEL end mode Non-3ST. Others 3ST. In differential mode PCI bus interface pins Other pins Input leakage current Input/output leakage current*2 Supply current 3ST. : Three-state mode *1 *2 : SCSI pins are; UDBP DB15 to DB8, LDBP DB7 to DB0, BSY, SEL, RST, ATN, REQ, ACK, MSG, C/D and , , I/O. (Total 27 pins) : Leak current when the three-state output pin output and the bidirectional bus pin output are in a high impedance state. 19 MB86606A 2. Input/Output Pin Capacitance (VDD = VIN = 0 V, f = 1 MHz, Ta = +25C) Conditions Symbol Unit Min. Max. CIN COUT Non-SCSI pins SCSI pins CI/O -- -- -- -- -- 12 8 10 10 25 pF pF pF pF pF Parameter Input-pin capacitance Output-pin capacitance Input/output-pin capacitance Pin name SCLK, PCLK (TP) Other input pins 3. Load Conditions for Measurement of AC Characteristics (1) Non-SCSI pins (VDD = +5 V5%, VSS = 0 V, Ta = 0 to +70C) Measurement point 16-bit bus mode Pin name INT, DREQ D15 to D8, UDP D7 to D0, LDP , , DMD15 to DMD8, UDMDP , DMD7 to DMD0, LDMDP PCI bus interface mode Pin name PCI bus pins CL 50 pF CL 60 pF 85 pF MB86606A Measurement pin CL (2) SCSI pins (VDD = +5 V5%, VSS = 0 V, Ta = 0 to +70C) Measurement point MB86606A Measurement pin R L1 Load resistance Load capacitance RL1 = 110 RL2 = 165 CL = 200 pF R L2 CL 20 MB86606A 4. AC Characteristics (1) System clock * SCSI clock (SCLK pin) Parameter Clock period Clock pulse width (Low) Clock pulse width (High) Clock pulse rise time Clock pulse fall time Symbol tCLF tCLCH tCHCL tCR tCF Value Min. 25.0 10.0 10.0 -- -- Typ. -- -- -- -- -- Max. 50.0 -- -- 5.0 5.0 Unit ns ns ns ns ns Note: When the internal operating clock frequency is the same as the input clock frequency, (when using the device in divide-by-1 mode), the clock pulse width for L and H levels must have minimum 20.0 ns or longer. (i.e. When the clock conversion register value is 0Bh (address: 10h in the initial setting registers) and input clock frequency = 20 MHz.) t CLCH t CF t CLF t CR 2.4 V 0.8 V 2.4 V 0.8 V SCLK 2.4 V 0.8 V 2.4 V 0.8 V t CHCL 21 MB86606A * PCI clock (PCLK pin) Parameter Clock frequency Clock pulse width (Low) Clock pulse width (High) Clock slew rate Clock amplitude Symbol tPCY tPLO tPHI tPSR VIHP - VILP Value Min. 30.0 12.0 12.0 1.0 2.0 Typ. -- -- -- -- -- Max. -- -- -- 4.0 -- Unit ns ns ns V/ns V t PHI t PCY V IHP PCLK 2.0 V 0.8 V 2.0 V 0.8 V 2.0 V 0.8 V 2.0 V 0.8 V V ILP t PLO (2) System reset Parameter Reset (RESET) pulse "L" level pulse width Symbol tWRSL Value Min. 4 tCLF Typ. -- Max. -- Unit ns t WRSL RESET 22 MB86606A 5. MPU Interface (1) Register write timing for 80 series Parameter Address (A4 to A0), BHE setup time (1) Address (A4 to A0) hold time (1) Address (A4 to A0), BHE setup time (2) Address (A4 to A0) hold time (2) CS0 setup time CS0 hold time Data set up time Data hold time WR "L" level pulse width Symbol tAWS tAWH tACS tACH tCWS tCWH tDWS tDWH tWR Value Min. 20 10 10 5 10 5 25 10 70 Max. -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns A4 to A0 BHE t AWS tACS t AWH t ACH CS0 t CWS t WR t CWH WR t DWS t DWH D15 to 8, UDP Data D7 to 0, LDP 23 MB86606A (2) Register read timing for 80 series Parameter Address (A4 to A0), BHE setup time (1) Address (A4 to A0) hold time (1) Address (A4 to A0), BHE setup time (2) Address (A4 to A0) hold time (2) CS0 setup time CS0 hold time RD set Low data output defined time RD set High data output defined time RD pulse duration at Low INT signal clear time Interrupt non-hold mode Interrupt hold mode Symbol tARS tARH tACS tACH tCRS tCRH tRLD tRHD tRD tDL tDL2 Value Min. 20 10 10 5 10 5 -- 5 70 -- -- Max. -- -- -- -- -- -- 40 -- -- 50 n*tCLF +50 Unit ns ns ns ns ns ns ns ns ns ns ns A4 to A0 BHE t ARS t ACS t ARH t ACH CS0 t CRS t RD t CRH RD t RLD t RHD D15 to 8, UDP Valid data D7 to 0, LDP INT t DL t DL2* (n is the division ratio) INT *: t DL2 is defined by the rising edge of strobe signal that reads out the step code for the last interrupt source. 24 MB86606A (3) Register write timing for 80 series (for external access) Parameter Address (A0), BHE setup time (1) Address (A0) hold time (1) Address (A0), BHE setup time (2) Address (A0) hold time (2) CS1 setup time CS1 hold time WR set Low DMA bus output delay time WR set High DMA bus output undefined time MPU data bus DMA bus output delay time Symbol tAWSE tAWHE tACSE tACHD tCWSE tCWHE tWHLD tWHHD tDHD Value Min. 20 10 10 5 10 5 -- 5 -- Max. -- -- -- -- -- -- 40 -- 20 Unit ns ns ns ns ns ns ns ns ns A0 BHE t AWSE t ACSE t AWHE t ACHD CS1 t CWSE t CWHE WR t WLHD t WHHD D15 to 8, UDP Data D7 to 0, LDP t DHD t DHD DMD15 to 8, UDMDP Valid data DMD7 to 0, LDMDP 25 MB86606A (4) Register read timing for 80 series (for external access) Parameter Address (A0), BHE setup time (1) Address (A0), BHE hold time (1) Address (A0), BHE setup time (2) Address (A0), BHE hold time (2) CS1 setup time CS1 hold time RD set Low MPU bus output enable time RD set High MPU bus output disable time DMA data bus MPU bus output delay time Symbol tARSE tARHE tACSE tACHD tCRSE tCRHE tRLNZ tRHHZ tHDD Value Min. 20 10 10 5 10 5 -- 5 -- Max. -- -- -- -- -- -- 40 -- 20 Unit ns ns ns ns ns ns ns ns ns A0 BHE t ARSE t ACSE t ARHE t ACHD CS1 t CRSE t CRHE RD DMD15 to 8, UDMDP DMD7 to 0, LDMDP t RLNZ Data t HDD t RHHZ Valid data D15 to 8, UDP D7 to 0, LDP 26 MB86606A (5) Register write timing for 68 series Parameter Address (A4 to A0) setup time (1) Address (A4 to A0) hold time (1) Address (A4 to A0) setup time (2) Address (A4 to A0) hold time (2) CS0 setup time CS0 hold time Data setup time Data hold time UDS/LDS "L" level pulse width R/W setup time R/W hold time Symbol tAWS tAWH tACS tACH tCWS tCWH tDWS tDWH tDS tRWS tRWH Value Min. 20 10 10 5 10 5 25 10 70 10 10 Max. -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns A4 to A0 t AWS t ACS t AWH t ACH CS0 t CWS t CWH R/W t RWS t DS t RWH UDS/LDS t DWS t DWH D15 to 8, UDP Data D7 to 0, LDP 27 MB86606A (6) Register read timing for 68 series Parameter Address (A4 to A0) setup time (1) Address (A4 to A0) hold time (1) Address (A4 to A0) setup time (2) Address (A4 to A0) hold time (2) CS0 setup time CS0 hold time Data output defined time Data output disable time UDS/LDS "L" level pulse width R/W setup time R/W hold time INT signal clear time Symbol tARS tARH tACS tACH tCRS tCRH tRLD tRHD tDS tRWS tRWH tDH tDH2 Value Min. 20 10 10 5 10 5 -- 5 70 10 10 -- -- Max. -- -- -- -- -- -- 40 -- -- -- -- 50 n*tCLK+50 Unit ns ns ns ns ns ns ns ns ns ns ns ns A4 to A0 t ARS t ACS t ARH t ACH CS0 t CRS t CRH R/W t RWS t DS t RWH UDS/LDS t RLD t RHD Valid data D15 to 8, UDP D7 to 0, LDP t DH INT (n is the division ratio) t DH2* INT *: t DH2 is defined by the rising edge of strobe signal that reads out the step code for the last interrupt source. 28 MB86606A (7) Register write timing for 68 series (for external access) Parameter Address (A0) setup time (1) Address (A0) hold time (1) Address (A0) setup time (2) Address (A0) hold time (2) CS1 setup time CS1 hold time UDS/LDS set Low DMA bus output delay time UDS/LDS set High DMA bus output undefined time MPU data bus DMA bus output delay time R/W setup time R/W hold time Symbol tAWSE tAWHE tACSE tACHD tCWSE tCWHE tWLHD tWHHD tDHD tRWS tRWH Value Min. 20 10 10 5 10 5 -- 5 -- 10 10 Max. -- -- -- -- -- -- 40 -- 20 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns A0 t AWSE t ACSE t AWHE t ACHD CS1 t CWSE t CWHE R/W t RWS t DS t RWH UDS/LDS t WHHD t WLHD D15 to 8, UDP Data D7 to 0, LDP t DHD DMD15 to 8, UDMDP Valid data DMD7 to 0, LDMDP 29 MB86606A (8) Register read timing for 68 series (for external access) Parameter Address (A0) setup time (1) Address (A0) hold time (1) Address (A0) setup time (2) Address (A0) hold time (2) CS1 setup time CS1 hold time UDS/LDS set Low MPU data bus output enable time UDS/LDS set High MPU data bus output disable time DMA bus MPU data bus output delay time R/W setup time R/W hold time Symbol tARSE tARHE tACSE tACHD tCRSE tCRHE tRLNZ tRHH tHDD tRWS tRWH Value Min. 20 10 10 5 10 5 -- 5 -- 10 10 Max. -- -- -- -- -- -- 40 -- 20 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns A0 t ARSE t ACSE t ARHE t ACHD CS1 t CRSE t CRHE R/W t RWS t RWH UDS/LDS DMD15 to 8, UDMDP DMD7 to 0, LDMDP t RLNZ t HDD Data t RHHZ Valid data D15 to 8, UDP D7 to 0, LDP 30 MB86606A 6. DMA Interface DMA access timing The time regulations are not applicable in the following cases: * * * * During SCSI input and when data buffer EMPTY, or when one byte held During SCSI output and when data buffer FULL, or when 511 bytes held When parity error detected (target) When error stopping transfer occurs in SCSI interface (1) Access cycle time (burst mode) Parameter Symbol tDCY1 Address cycle time tDCY2 tDCY3 tDCY4 Value Min. 2 tCLF 3 tCLF 4 tCLF 1 tCLF Max. -- -- -- -- Unit ns ns ns ns t DCY2 IOWR/IORD DMUDS/DMLDS t DCY1 t DCY4 t DCY3 31 MB86606A (2) Write timing (burst mode for 80 series) Parameter DREQ set High DACK set Low IOWR set Low DREQ set Low DREQ set Low DREQ set High DACK set Low IOWR set Low DMBHE, DMA0 setup time IOWR "L" level pulse width IOWR set High DACK set High DMBHE, DMA0 hold time Input data setup time Input data hold time Symbol tDHAL tALDL tDLDH tALWL tDAWS tDWR tWHAH tDAWH tDDWS tDDWH Value Min. 0 -- 0 0 10 25 0 10 25 5 Max. -- 25 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns t DLDH DREQ t DHAL t ALDL DACK t ALWL t WHAH DMBHE DMA0 t DAWS t DWR t DAWH IOWR t DDWS t DDWH DMD15 to 0 UDMDP, LDMDP Data 32 MB86606A (3) Read timing (burst mode for 80 series) Parameter DREQ set High DACK set Low IORD set Low DREQ set Low DREQ set Low DREQ set High DACK set Low IORD set Low DMBHE, DMA0 setup time IORD "L" level pulse width IORD set High DACK set High DMBHE, DMA0 hold time Data output defined time Data output hold time Symbol tDHAL tALDL tDLDH tALRL tDARS tDRD tRHAH tDARH tDRLD tDRHD Value Min. 0 -- 0 0 10 25 0 10 -- 10 Max. -- 25 -- -- -- -- -- -- 25 -- Unit ns ns ns ns ns ns ns ns ns ns t DLDH DREQ t DHAL t ALDL DACK t ALRL t RHAH DMBHE DMA0 t DARS t DRD t DARH IORD t DRLD t DRHD Valid data DMD15 to 0 UDMDP, LDMDP 33 MB86606A (4) Write timing (burst mode for 68 series) Parameter DREQ set High DACK set Low DMUDS/DMLDS set Low DREQ set Low DREQ set Low DREQ set High DACK set Low DMUDS/DMLDS set Low R/W setup time DMUDS/DMLDS "L" level pulse width DMUDS/DMLDS set High DACK set High R/W hold time Input data setup time Input data hold time Symbol tDHAL tALDL tDLDH tALDL tDRWS tDDS tDHAH tDRWH tDDWS tDDWH Value Min. 0 -- 0 5 10 25 0 10 25 5 Max. -- 25 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns t DLDH DREQ t DHAL t ALDL DACK t ALDL t DHAH DMR/W t DRWS t DDS t DRWH DMUDS/DMLDS t DDWS t DDWH DMD15 to 0 UDMDP, LDMDP Data 34 MB86606A (5) Read timing (burst mode for 68 series) Parameter DREQ set High DACK set Low DMUDS/DMLDS set Low DREQ set Low DREQ set Low DREQ set High DACK set Low DMUDS/DMLDS set Low R/W setup time DMUDS/DMLDS "L" level pulse width DMUDS/DMLDS set High DACK set High R/W hold time Output data valid time Output data hold time Symbol tDHAL tALDL tDLDH tALDL tDRWS tDDS tDHAH tDRWH tDRLD tDRHD Value Min. 0 -- 0 5 10 25 0 10 -- 10 Max. -- 25 -- -- -- -- -- -- 25 -- Unit ns ns ns ns ns ns ns ns ns ns t DLDH DREQ t DHAL t ALDL DACK t ALDL t DHAH DMR/W t DRWS t DDS t DRWH DMUDS/DMLDS t DRLD t DRHD Valid data DMD15 to 0 UDMDP, LDMDP 35 MB86606A 7. PCI Interface (1) PCI interface signal timing Parameter Output signal valid time Output disable time Output enable time Input setup time Input hold time *1: Applicable to PREQ pin *2: Applicable to GNT pin Symbol tPVAL tPOFF tPON tPSU tPHD Value Min. 2 -- 2 7/10*2 0 Max. 11/12*1 28 -- -- -- Unit ns ns ns ns ns 2.4 V PCICLK 1.5 V 0.4 V OUTPUT H to I or L to H t PVAL 1.5 V OUTPUT H/L to Hi-Z t POFF OUTPUT Hi-Z to H/L t PON 2.4 V INPUT 1.5 V 1.5 V 0.4 V t PSU t PHD 36 MB86606A (2) Configuration register read timing PCICLK FRAME IDSEL AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL STOP (3) Configuration register write timing PCICLK FRAME IDSEL AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL STOP Note: For the access to the configuration register, only one data transfer possible. When a master device executes the burst transfer, a target device asserts STOP signal, and performs the target termination. 37 MB86606A (4) BASIC control register read timing (target mode) * Byte or word access Burst read (target termination), single read PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL STOP Note: Only one data transfer is possible for reading BASIC control regisuter. When a master device does the burst transfer to the target device, it asserts STOP signal and performs the target termination. 38 MB86606A * Long-word access Single read PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL STOP Burst read (target termination) PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL STOP Note: For the read operation of BASIC control registers, only one data transfer possible. When a master device executes the burst transfer, a target device asserts STOP signal and performs the target termination. 39 MB86606A (5) Target mode - I/O, memory read timing (except BASIC control registers) * Byte, word access Single read PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL Burst read PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL 40 MB86606A * Long-word access Single read PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL Burst read PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL 41 MB86606A (6) Target Mode - I/O, memory write timing * Byte, word access Single write burst write PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL 42 MB86606A * Long-word access Single write PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL Burst write PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL 43 MB86606A (7) Data read timing (master mode) * Burst length = 1 and 4 Burst = 1 PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL Burst = 4 * Burst length = 8 PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL * Burst length = 16 PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL 44 MB86606A (8) Data write timing (master mode) * Burst length = 1 and 4 Burst = 1 PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL Burst = 4 * Burst length = 8 PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL * Burst length = 16 PCICLK FRAME AD31 to 00 C/BE3 to 0 IRDY TRDY DEVSEL 45 MB86606A 8. SCSI Interface (1) Initiator asynchronous input timing (target initiator) Parameter ACK set Low REQ set High REQ set High ACK set High ACK set High REQ set Low Data bus valid REQ set Low REQ set Low data bus hold time REQ set Low ACK set Low REQ set High ACK set Low* Symbol tAOLR tRAOH tAOHR tDTSU tDHLD tRAOL tRACY Value Min. 0 -- 10 10 20 -- -- Max. -- 60 -- -- -- 40 3 tCLF +40 Unit ns ns ns ns ns ns ns * : tRACY (REQ set High ACK set Low) is defined as either longer time of (tRAOH + tAOHR +tRAOL) or tRACY itself Note: Time requirements in this section do not apply in the following cases; * When data register FULL in data phase * When last byte transferred t RACY REQ t AOLR t RAOH t AOHR t RAOL ACK t DTSU t DHLD Data DB7 to 0, P DB15 to 8, P 46 MB86606A (2) Initiator asynchronous output timing (initiator target) Parameter ACK set Low REQ set High REQ set High ACK set High ACK set High REQ set Low Data bus output defined ACK set Low* REQ set High data bus hold time REQ set Low ACK set Low Symbol tAOLR tRAOH tAOHR tDVLD tDIVD tRAOL Value Min. 0 -- 10 S*tCLF-10 2 tCLF -- Max. -- 60 -- -- -- 40 Unit ns ns ns ns ns ns * : The value of S varies with the setting condition of the asynchronous setup time register (address 17h). Note: This output timing regulations are not applicable when the data register is EMPTY in the data phase. t RACY* REQ t AOLR t RAOH t AOHR t RAOL ACK t DVLD t DIVD Valid data t DVLD Valid data DB7 to 0, P DB15 to 8, P * : The time (tRACY) of REQ set High ACK set Low is defined by the longer time either (tRAOH + tAOHR +tRAOL) or (tDIVD + tDVLD). 47 MB86606A (3) Initiator synchronous transfer REQ/ACK timing Parameter ACK Assertion Period* ACK Negation Period* REQ Assertion Period REQ Negation Period REQ input cycle time (1) REQ input cycle time (2) Symbol tAKAP tANAP tRQAP tRNAP tRQF1 tRQF2 Value Min. A*tCLF-4 N*tCLF-6 20 20 1 tCLF 3 tCLF Max. -- -- -- -- -- -- Unit ns ns ns ns ns ns * : The values of A and N vary with the setting condition of the transfer period register (address 0Ch). t AKAP t ANAP ACK t RQAP t RNAP REQ t RQF1 t RQF2 48 MB86606A (4) Initiator synchronous transfer input timing (target initiator) Parameter Data bus defined REQ set Low REQ set Low data bus hold time Symbol tDTSU tDHLD Value Min. 5 15 Max. -- -- Unit ns ns REQ t DTSU t DHLD Data t DTSU Data t DHLD DB7 to 0, P DB15 to 8, P (5) Initiator synchronous transfer output timing (initiator target) Parameter Data bus defined ACK set Low* ACK set Low data bus hold time* Symbol tDVAK tAKDH Value Min. N*tCLF-10 A*tCLF-5 Max. -- -- Unit ns ns * : The values of A and N vary with the setting condition of the transfer period register (address 0Ch). ACK t DVAK t AKDH t DVAK Valid data t AKDH DB7 to 0, P DB15 to 8, P Valid data 49 MB86606A (6) Target asynchronous input timing (initiator target) Parameter REQ set Low ACK set Low ACK set Low REQ set High REQ set High ACK set High Data bus defined ACK set Low ACK set Low data bus hold time ACK set High REQ set Low ACK set Low REQ set Low* Symbol tROLA tAROH tROHA tDTSU tDHLD tAROL tRACY Value Min. 0 -- 0 10 20 -- -- Max. -- 60 -- -- -- 40 3 tCLF + 40 Unit ns ns ns ns ns ns ns * : tRACY (ACK set Low REQ set Low) is defined as either longer time of (tAROH + tROHA +tAROL) or tRACY itself Note: The input timing regulations are not applicable when the data register is FULL in the data phase. t RACY REQ t ROLA t AROH t ROHA t AROL ACK t DTSU t DHLD Data DB7 to 0, P DB15 to 8, P 50 MB86606A (7) Target asynchronous input timing (target initiator) Parameter REQ set Low ACK set Low ACK set Low REQ set High REQ set High ACK set High Data bus defined REQ set Low* ACK set Low data bus hold time ACK set High REQ set Low Symbol tROLA tAROH tROHA tDVLD tDIVD tAROL Value Min. 0 -- 0 S*tCLF - 10 2 tCLF -- Max. -- 60 -- -- -- 40 Unit ns ns ns ns ns ns * : The value of S varies with the setting condition of the asynchronous setup time register (address 17h). Note: The output timing regulations are not applicable when the data register is EMPTY in the data phase. t RACY* REQ t ROLA t AROH t ROHA t AROL ACK t DVLD t DIVD Valid data t DVLD Valid data DB7 to 0, P DB15 to 8, P * : The time (tRACY) of ACK set High REQ set Low is defined by the longer time either (tAROH + tROHA +tAROL) or (tDIVD + tDVLD). 51 MB86606A (8) Target synchronous transfer REQ/ACK timing Parameter REQ Assertion Period* REQ Negation Period* ACK Assertion Period ACK Negation Period ACK input cycle time (1) ACK input cycle time (2) Symbol tRQAP tRNAP tAKAP tANAP tAKF1 tAKF2 Value Min. A*tCLF - 4 N*tCLF - 6 20 20 1 tCLF 3 tCLF Max. -- -- -- -- -- -- Unit ns ns ns ns ns ns * : The values of A and N vary with the setting condition of the transfer period register (address 0Ch). t RQAP t RNAP REQ t AKAP t ANAP ACK t AKF1 t AKF2 52 MB86606A (9) Target synchronous transfer input timing (initiator target) Parameter Data bus defined ACK set Low ACK set Low data bus hold time Symbol tDTSU tDHLD Value Min. 5 15 Max. -- -- Unit ns ns ACK t DTSU t DHLD Data t DTSU Data t DHLD DB7 to 0, P DB15 to 8, P (10) Target synchronous transfer output timing (target initiator) Parameter Data bus defined REQ set Low* REQ set Low data bus hold time* Symbol tDVRQ tRQDH Value Min. N*tCLF - 10 A*tCLF - 5 Max. -- -- Unit ns ns * : The values of A and N vary with the setting condition of the transfer period register (address 0Ch). REQ t DVRQ t RQDH t DVRQ t RQDH DB7 to 0, P DB15 to 8, P Valid data Valid data 53 MB86606A (11) A, N, and S values in SCSI interface timing specifications * Set value for transfer period register and A, N values Transfer period register 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A (inhibited) 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 N (inhibited) 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 Transfer period register 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 N 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 Note: The A and N values in the register setting represent the assertion and negation periods (in clock-cycle units). The numerical value is applicable to the A and N values in AC characteristics. 54 MB86606A * Set value for asynchronous setup time register and S value Asynchronous setup time setting register 3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note: The S (setup time) value of the setup time setting register in asynchronous data transfer represents the time required to assert the REQ or ACK signal after setting data at the data bus (in clock-cycle units). The numerical value is applicable to the S value in AC characteristics. 55 MB86606A s SYSTEM CONFIGURATION 1. 80-Series Separate Bus Type MB86606A OSC RESET circuit CLK DB15 to 8 RESET UDBP DB7 to 0 MODE0 LDBP MODE1 DBOE15 to 8 UDBOEP DBOE7 to 0 LDBOEP INT MPU CS0 ACK CS1 ATN ADDRESS DECODE DIFFERENTIAL INIT A4 to A0 ADDRESS BUS REQ MSG C/D I/O TARG BHE RD WR DMD15 to 0 UDMDP LDMDP D15 to D0 UDP LDP DATA BUS DR/REV DMA BUS BSY BSYOE DREQ DACK DMBHE IORD IOWR DMA CONTROL ADDRESS DATA BUFFER MEMORY SEL SELOE RST RSTOE DMA0 TP SDSEL 56 MB86606A 2. 68-Series Separate Bus Type MB86606A OSC RESET circuit CLK DB15 to 8 RESET UDBP DB7 to 0 MODE0 LDBP MODE1 DBOE15 to 8 UDBOEP DBOE7 to 0 LDBOEP INT A0 CS0 MPU ACK CS1 DIFFERENTIAL ADDRESS DECODE ATN INIT A4 to A1 ADDRESS BUS REQ MSG C/D I/O TARG DR/REV D15 to D0 UDP LDP R/W UDS LDS DMD15 to 0 UDMDP LDMDP DATA BUS DMA BUS BSY BSYOE DREQ DACK DMR/W DMUDS DMLDS DMA CONTROL ADDRESS DATA BUFFER MEMORY SEL SELOE RST RSTOE DMA0 TP SDSEL 57 MB86606A 3. 80-Series Common Bus Type MB86606A OSC RESET circuit CLK DB15 to 8 RESET LDBP DB7 to 0 MODE0 UDBP MODE1 DBOE15 to 8 UDBOEP DBOE7 to 0 LDBOEP INT MPU CS1 ACK CS0 ATN ADDRESS DECODE DIFFERENTIAL INIT A4 to A0 ADDRESS BUS REQ MSG C/D I/O TARG BHE RD WR DMD15 to 0 UDMDP LDMDP D15 to D0 UDP LDP DATA BUS DR/REV DMA BUS BSY BSYOE DREQ DACK DMBHE IORD IOWR DMA CONTROL SEL SELOE RST RSTOE DMA0 TP SDSEL 58 MB86606A 4. 68-Series Common Bus Type MB86606A OSC RESET circuit CLK DB15 to 8 RESET LDBP DB7 to 0 MODE0 UDBP MODE1 DBOE15 to 8 UDBOEP DBOE7 to 0 LDBOEP INT A0 CS1 MPU ACK CS0 ATN ADDRESS DECODE DIFFERENTIAL INIT A4 to A1 ADDRESS BUS REQ MSG C/D I/O DR/REV D15 to D0 UDP LDP R/W UDS LDS DMD15 to 0 UDMDP LDMDP DATA BUS TARG DMA BUS BSY BSYOE DREQ DACK DMR/W DMUDS DMLDS DMA CONTROL SEL SELOE RST RSTOE DMA0 TP SDSEL 59 MB86606A 5. Example of Connection in Differential Mode (Example of Driver/Receiver Connection) (TOP VIEW) RO 1 R RE 2 DE 3 DI 4 D 8 V CC 7 DO, RI 6 DO, RI 5 GND MB561 MB86606A 18 DB15 to 0 UDBP LDBP 18 DBOE15 to 0 UDBOEP LDBOEP (-) SIGNAL D R (+) SIGNAL 2 ACK, ATN R (+) SIGNAL INIT D (-) SIGNAL 4 REQ, MSG C/D, I/O R (+) SIGNAL TARG (-) SIGNAL D BSY, SEL RST 3 R 3 (-) SIGNAL D (+) SIGNAL BSYOE, SELOE RSTOE SDSEL 60 SCSI BUS MB86606A 6. Example of Connection in Single-end Mode MB86606A DB15 to 0 UDBP LDBP DBOE15 to 0 UDBOEP LDBOEP 18 18 (OPEN) 2 ACK, ATN INIT (OPEN) SCSI BUS 4 REQ, MSG C/D, I/O TARG (OPEN) BSY, SEL RST 3 BSYOE, SELOE RSTOE SDSEL 3 (OPEN) 61 MB86606A s ORDERING INFORMATION Part number MB86606APMT2 Package 144-pins, Plastic LQFP (FPT-144P-M08) Remarks 62 MB86606A s PACKAGE DIMENSION 144-pin plastic LQFP (FPT-144P-M08) 22.000.30(.866.012)SQ 20.000.10(.787.004)SQ 1.70(.67)MAX (Mounting height) 73 72 108 109 0(0)MIN (STAND OFF) 17.50 (.686) REF INDEX 144 37 21.00 (.827) NOM Details of "A" part 0.15(.006) 0.15(.006) 0.15(.006)MAX 0.40(.016)MAX "A" LEAD No. 1 36 Details of "B" part M 0.50(.0197)TYP 0.200.10 (.008.004) 0.08(.003) 0.150.05 (.006.002) 0 10 0.10(.004) 0.500.20(.020.008) "B" C 1995 FUJITSU LIMITED F144019S-1C-2 Dimensions in mm (inches) 63 MB86606A FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9904 (c) FUJITSU LIMITED Printed in Japan 64 |
Price & Availability of MB86606A
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |